1. Technical Field
Embodiments of the invention relate generally to interrupts for processors.
2. Background Art
An Advanced Programmable Interrupt Controller (APIC) is a programmable interrupt controller (PIC) that receives interrupt requests and provides interrupt outputs according to programmable procedures or priorities. Local APICs are used in processors (such as microprocessors). I/O APICs are used in chipset devices (such as an input/output (I/O) controller hub (ICH)) and peripheral devices. Examples of peripheral devices include device coupled to the ICH that are compatible with one of the Peripheral Component Interconnect (PCI) standards or one of the PCI Express (PCIe) standards such as the PCI Express® Base Specification Revision 2.0, Dec. 20, 2006, provided by the PCI-SIG®. An xAPIC is an extended APIC, which is similar to early APICs but with some additional features and in the xAPIC architecture, local and I/O APICs communicate through a system bus rather than through an APIC bus. A further Extended xAPIC includes additional extensions and features.
Processor packages may include more than one core, each of which may include more than one processor. Physical mode interrupts are interrupts for which an interrupting device designates a processor by a physical identification number or is broadcast to all processors. Logical mode interrupts are interrupts for which an interrupting device designates a processor or processors by a logical identification numbers or numbers. APIC interrupt deliveries include directed interrupts (single processor target), multi-cast (multiple processor target) and broadcast (all processors). In a lowest priority or re-directable interrupt, a procedure is used to select a processor that is in the lowest processor priority to respond to the interrupt. This feature allows for an interrupt source (specifically a device) to specify multiple processors as potential targets for an interrupt and at the time of interrupt delivery have the platform hardware choose the “lowest priority” processor from the set of identified processors for delivery. The lowest priority is based on an operating system (OS) programmable processor priority that reflects the criticality of the work being performed on the CPU. Lowest priority may be decided in the chipset—often in an ad hoc fashion or with stale data of processor priority. Because the priority information is often not reliable, some chipsets merely select a particular processor (such as through a round robin technique) and provide the interrupt to that processor in a broadcast manner in which the other processors also receive the interrupts but do not respond to them.
The logical mode provides significantly greater flexibility in directed interrupts and is the mode used by Microsoft Windows & some Linux shrink-wrap operating systems. The logical mode of the xAPIC architecture provides an operating system software with flexibility in initializing the logical APIC identification number (ID), which is the unique identifier for each processor in the system. (The processors also have physical APIC IDs.) Other processors as well as devices or IOxAPICs use this ID to send interrupts to this processor. Given the flexibility in initialization of the logical xAPIC ID, there is no relationship between the actual physical topology of the platform and how the IDs are assigned. Although operating system initialization allows operating systems greater flexibility in grouping processors, at a platform level this complicates the routing of directed logical mode interrupts. Routing of logical mode interrupts is done through broadcasting the interrupts and having the local processor logic accept the interrupt if it matches its local APIC ID.
Many processors include a task priority register (TPR) that holds a task priority selected by software that allows the software to set a priority threshold for interrupting the processor. The processor will service only those interrupts that have a priority higher than that specified in the TPR. For example, if software sets the task priority in the TPR to 0, the processor will handle all interrupts; if it is set to 15, all interrupts are inhibited from being handled by that processor (with some exceptions). In some processors, including some processors manufactured by Intel Corporation, the TPR has 32 bits, with address FEE00080H, where H=hexadecimal. Bits 0 to 3 designate a task priority sub-class, bits 4 to 7 designate a task priority, and bits 8 to 31 are reserved. However, currently only bits 0-3 of the TPR are used to specify a priority of between 0 and 15, with bits 4-7 being unused. In some processors, a TPR is located in a local APIC in the processor. A processor priority registers (PPR) may hold a processor priority used to determine whether a pending interrupt can be dispensed to the processor.
Many computer systems have multiple interrupt vectors (such as 256 interrupt vectors with 16 groups of 16 interrupt vectors) pointed to by an interrupt descriptor table. A deferred procedure call (DPC) is a mechanism that allows a processor which is current executing a task to perform less critical tasks by deferring their execution. Many processors have power states referred to as C states, such as C0, C1, etc., where C0 is a lower power state than a high numbered C state such as C2. In some computer systems, different priorities have different meanings. For example, a priority 0 may called passive, priority 3 may called referred to as asynchronous procedure call (APC) priority, priority 4 may be referred to as a DPC priority, priorities 5-B are for devices, priority C is clocks, priority D is for inter-processor interrupts (IPIs), and priorities E and F are for other things. Other schemes are different meanings for priorities. For example, in some schemes, priority 3 is a DPC priority.
In some operating systems, the software priority scheme does not necessarily map well on to the xAPIC priority scheme. In these operating systems, there may be a priority inversion, where, for example, an idle processor can end up at a higher priority than processors doing work. Additionally, because of power management using different C-State, some idle processors (ones in deeper C-States) may be less suitable to service interrupts (take longer to respond and require more power) than others, but all of these processors are at the same priority level.